An example of a reproduced signal processing circuit in a conventional optical disk apparatus is shown in FIG. 23.
In FIG. 23, 1 is a recording medium such as an optical disk, 2 is an optical pick-up, 3 is an analog front end, and 12 is a digital signal processing circuit. In the digital signal processing circuit 12 mentioned above, 4 is an A/D converter, 5 is a digital filter, 6 is a decoder, and 13 is a synchronous clock extracting circuit. In the synchronous clock extracting circuit 13 mentioned above, 7 is a phase comparator, 8 and 11 are loop filters, 9 is a VCO (voltage control oscillator), and 10 is a frequency comparator. A description will be given herein below to the detail of the foregoing structure and to the outline of the operation thereof.
When data written in the recording medium 1 such as an optical disk is to be reproduced therefrom, a laser beam is applied to the recording medium 1 first, the reflected beam is picked up therefrom by using the optical pick-up 2, and the intensity of the reflected light is converted to an electric signal so that an analog reproduced signal is generated. The analog reproduced signal obtained by using the optical pick-up 2 is subjected to the gain adjustment of the signal amplitude and DC offset adjustment in an analog front end 3 and further to the boosting of the RF component and a noise removal process, each performed therein for the purpose of waveform equalization. The analog reproduced signal subjected to the waveform equalization in the analog front end 3 is quantized in the A/D converter 4 to provide digital data. Hereinafter, digital signal processing is performed in the subsequent stages.
In the digital signal processing circuit 12, the reproduced data quantized in the A/D converter 4 is subjected to a waveform correcting process through the digital filter 5 and decoded by the decoder 6 to provide binary data. The reproduced data quantized in the A/D converter 4 is also inputted to the synchronous clock extracting circuit 13.
In the synchronous clock extracting circuit 13, the frequency comparator 10 calculates a frequency error between the reproduced data and the clock outputted from the VCO 9, while the loop filter 11 filters the frequency error outputted from the frequency comparator 10. The VCO 9 changes the frequency of the clock outputted therefrom in accordance with the value of the frequency error smoothed by the loop filter 11. Likewise, the phase comparator 7 calculates the phase error between the reproduced data and the clock outputted from the VCO 9 and the loop filter 8 filters the phase error outputted from the phase comparator 7. The VCO 9 changes the frequency of the clock outputted therefrom in accordance with the value of the phase error smoothed by the loop filter 8. This feedback loop performs a control operation such that each of the frequency error and phase error of the clock outputted from the VCO 9 becomes zero. The synchronous clock extracting circuit 13 operates to perform frequency error correction first and then perform phase error correction. The clock outputted from the VCO 9 is supplied also to the digital signal processing circuit 12 including the A/D converter 4. When each of the frequency control and the phase control comes into a steady state, the output clock from the VCO 9 becomes a synchronous clock which is synchronized with the reproduced data.
A conventional structure of the phase comparator 7 in such a synchronous clock extracting circuit is disclosed in, e.g., Japanese Laid-Open Patent Publication No. HEI 8-17145. An example of the conventional structure of the phase comparator 7 will be shown herein below in FIG. 24.
In the drawing, the phase comparator 7 is composed of a zero cross detecting circuit 74 and a phase error calculating circuit 75. The zero cross detecting circuit 7 detects a zero cross point from the reproduced data and outputs a zero cross detection signal. The phase error calculating circuit 75 receives the reproduced data and the zero cross detection signal as an input signal and an enable signal, respectively, and outputs phase error data at the timing of the zero cross detection signal.
Subsequently, an example of the conventional structure of the zero cross detecting circuit 74 will be shown in FIG. 25. The zero cross detecting circuit 74 in the drawing is composed of an averaging circuit 741, a D flip-flop 742, and an EXCUSIVE-OR circuit 743. The averaging circuit 741 calculates an average value of two consecutive items of reproduced data and outputs the sign data thereof. The D flip-flop 742 delays the sign data from the averaging circuit 741 by a period corresponding to 1 clock. The sign data EXCLUSIVE-OR circuit 743 receives two sign data items which are the sign data of the average value outputted from the averaging circuit 741 and the sign data delayed in the D flip-flop 742 and detects points at which the signs of the sign data items are inverted from a positive value to a negative value and from a negative value to a positive value. An output from the EXCLUSIVE-OR circuit 743 is used as the zero cross detection signal from the zero cross detecting circuit 74.
An example of the outline of zero cross point detection in the zero cross detecting circuit 74 is shown in FIG. 26. The drawing shows the outline of zero cross point detection upon the rising of reproduced data. The circular marks indicate sampling points for the reproduced data, which are represented as a(n−1), a(n), and a(n+1) with a lapse of time. The zero cross point detected as a phase error in this case is a(n). Each of the crossed (X) marks indicates an average value of two consecutive sign data items. Since the average value of the sign data a(n−1) and the subsequent sign data a(n) has a positive sign and the average value of the sign data a(n) and the subsequent sign data a(n+1) has a negative sign, the sign data a(n) in the middle is determined to be the zero cross point. The phase error is calculated based on the value of the sign data a(n) and the direction of a cross edge.
Problem to be Solved
The problem of a conventional zero cross detection method is shown in FIGS. 27(a) and 27(b). The drawings show the outline of zero cross detection performed with respect to a (3T+3T) reproduced waveform (T is a channel cycle period), of which FIG. 27(a) shows the outline of zero cross detection that has been performed normally by using the zero cross detection method illustrated with reference to FIG. 26. As can be seen from the drawing, a zero cross point is detected correctly when the reproduced data and the sampling clock are in synchronization. By contrast, when a frequency error between the reproduced data and the sampling clock is large as shown in FIG. 27(b), phase inversion occurs at a given point so that the zero cross point is detected erroneously.
Thus, the conventional phase error comparison method has the problem of a narrow capture range due to a narrow input linear range.